1. Field of the Invention
The present invention generally relates to interface circuits for a semiconductor device, and more particularly, to an interface circuit for a semiconductor device in which reflected waves on a bus are efficiently suppressed even when there is an impedance mismatching between the semiconductor device and a bus, and in which an overshoot and a glitch, a form of waveform distortion, occurring in data or control information transmitted on a bus are efficiently suppressed, the overshoot being responsible for preventing a high-speed operation and the glitch causing an error.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional technology used to connect semiconductor devices 13 and 14 with a bus 11 via input terminals 12.
As shown in FIGS. 1 and 2, a core circuit 20 for exchanging data via an input/output circuit with external devices and executing a predetermined process (for example, numerical operation or storage of data) on the data, and a plurality of bonding pads that enable the core circuit 20 to exchange signals with external devices are provided on an IC chip of the semiconductor device such as an MPU or a memory. In the IC chip of the MPU, the input terminals 12 are bonded to the respective bonding pads with a bonding wire having an impedance Z1. In the IC chip of the memory, the input terminals 12 are bonded to the respective bonding pads with a bonding wire having an impedance Z5. Each of the IC chips is hermetically sealed in a package so as to constitute a module. Each module is referred to as a MPU chip or a memory chip.
The MPU chip is connected to the bus 11 having an impedance Z2 via a module wiring having an impedance Z2 formed on a printed circuit board or the like so as to form an electric circuit. The memory chip is connected to the bus 11 having an impedance Z3 via a module wiring having an impedance Z4 formed on a printed circuit board or the like. The bus 11 may include a data bus line for transmitting data and a control bus line for transmitting control information such as address information or control instructions. The bus 11 formed on the printed circuit board may be 16-bit wide, 32-bit wide or 64-bit wide, depending on the number of input/output bits or the processing power of the MPU. The same thing is true of the bus 11 connected to the memory. FIG. 2 shows only the electric connection involving bus lines for 1 bit. The other bus lines omitted in FIG. 2 carrying the other bits are provided similarly and have the same respective impedance.
Due to a impedance mismatching occurring between the semiconductor device (the MPU chip or the memory chip) and the bus 11, an overshoot or a waveform distortion in the form of a glitch as shown in FIG. 3 occurs. Referring to FIG. 3, an overshoot refers to an excess in the level of data or control information transmitted over the bus 11 beyond a potential level V.sub.cc of a power supply of the semiconductor device. A certain time is required before the overshoot or the glitch is attenuated so that the data or the control information is identified on the bus 11. For this reason, as shown in FIG. 3, there is a demand to suppress an overshoot at time t1 and suppress generation of a reflected wave after time t2.
One conventional approach to attenuate the overshoot or the glitch in a short period of time is to provide a filter circuit between the MPU chip or the memory chip and the bus 11. Alternatively, a gate circuit having a predetermined number of stages for cutting off the overshoot or the glitch may be provided in the input/output circuit.
However, providing a filter circuit or a gate circuit to suppress the overshoot or the glitch prevents switching between signals from occurring on the bus 11 at a short period and prevents the semiconductor device from operating at a high-speed. Another problem with the conventional approach is that extra elements and circuits have to be introduced, thus increasing power consumption. Providing filters or gate circuits operating satisfactorily for each of a variety of semiconductor devices and the bus line 11 connected thereto requires a complicated design.